Digital signal buffer circuit

ABSTRACT

A delay circuit is provided with a plurality of variously sized equalization transistors, a plurality of equalization resistors having different resistance values, a plurality of equalization capacitors having difference capacitance values, and switch circuits. The switch circuits are used to make selections from among the equalization transistors, equalization resistors, and equalization capacitors for the purpose of adjusting the amplitude level and delay amount of a digital inverse signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a digital signal buffer circuit that isused, for instance, in a communication system for digital signaltransmission, to generate an output in which a digital signal change isemphasized.

2. Background Art

A communication system disclosed, for instance, by Japanese PatentLaid-open No. 204291/2003 is provided with a transmission circuit thatis mounted at the transmitting end of a communication systemtransmission path, and a reception circuit that is mounted at thereceiving end of the communication system transmission path. Thetransmission circuit and reception circuit are both provided with anequalization circuit. The transmission circuit and reception circuitboth include a digital signal buffer circuit. The buffer circuit havingan equalization circuit adds a delayed, small-amplitude digital inversesignal to an input digital signal and generates an output digitalsignal, in which an input digital signal change is emphasized, toprovide improved communication performance.

SUMMARY OF THE INVENTION

The present invention relates to a digital signal buffer circuit havingthe above-mentioned type of equalization circuit, and provides a digitalsignal buffer circuit that is improved to permit level adjustments overa wider bandwidth.

The above objects of the present invention are achieved by a digitalsignal buffer circuit, which includes an equalization circuit forgenerating a digital inverse signal that is delayed from an inputdigital signal and obtained by inverting the input digital signal. Theequalization circuit includes a plurality of variously-sizedequalization transistors. The equalization circuit also includes a delaycircuit capable of changing the delay amount. The equalization circuitfurther includes a switching circuit for switching between the pluralityof transistors and changing the delay amount of the delay circuit.

The above objects of the present invention are achieved by a digitalsignal buffer circuit. The digital signal buffer circuit includes afirst buffer for receiving an input digital signal, a second buffer forreceiving the output of the first buffer, and a third buffer forgenerating an output digital signal upon receipt of an output from thesecond buffer. The second buffer includes an equalization transistor,which generates a digital inverse signal that is obtained by invertingthe input digital signal and delayed. The second buffer also includesswitches between a first feedback line for feeding the output of thesecond buffer back to the equalization transistor and a second feedbackline for feeding the output of the third buffer back to the equalizationtransistor.

The above objects of the present invention are achieved by a digitalsignal buffer circuit. The digital signal buffer circuit includes afirst buffer for receiving an input digital signal, and a second bufferfor generating an output digital signal upon receipt of an output fromthe first buffer. The second buffer includes an equalization transistorfor generating a digital inverse signal that is obtained by invertingthe input digital signal and delayed. The digital signal buffer circuitforms a delay path between the output of the first buffer and theequalization transistor, which includes a switch and a low-pass filter.

Other objects and further features of the present invention will beapparent from the following detailed description when read inconjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a first embodiment of a digital signal buffer circuitaccording to the present invention;

FIG. 2 is the details of the equalization circuit;

FIG. 3A to FIG. 3C show the amplitude adjustment of the digital signal;

FIG. 4A to FIG. 4C show the delay amount adjustment of the digitalsignal;

FIG. 5 is the transfer gate circuit TG;

FIG. 6 is a fourth embodiment of the digital signal buffer circuitaccording to the present invention; and

FIG. 7 is a fifth embodiment of the digital signal buffer circuitaccording to the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments of the present invention will now be described withreference to the accompanying drawings.

FIRST EMBODIMENT

FIG. 1 illustrates a first embodiment of a digital signal buffer circuitaccording to the present invention. FIG. 2 shows the details of itsequalization circuit.

The digital signal buffer circuit 100 according to the first embodimentis used, for instance, in a reception circuit that is connected to theoutput end of a digital transmission path. The buffer circuit 100according to the first embodiment includes an input terminal 101, anoutput terminal 102, an input stage buffer 10, an output stage buffer20, and an equalization circuit 30. The input stage buffer 10, outputstage buffer 20, and equalization circuit 30 are connected between theinput terminal 101 and output terminal 102. The buffer circuit 100 ismade of a semiconductor integrated circuit.

The input stage buffer 10 includes a pair of transistors M1, M2, a pairof resistors 11, 12, and a constant current source 15. For example, thetransistors M1, M2 are N-channel MOS transistors. Their sources areconnected to a positive potential line VDD via the resistors 11, 12.Their drains are mutually interconnected and connected to a referencepotential such as a ground potential via the constant current source 15.The gates of the pair of transistors M1, M2 are connected to the inputterminal 101 of the buffer circuit 100 via a pair of input lines Lin. Aninput digital signal Vin such as an input digital data signal issupplied to the input terminal 101. The junction between resistor 11 andthe source of transistor M1 and the junction between resistor 12 and thesource of transistor M2 are connected to connection lines L1 and L2,respectively. The input stage buffer 10 outputs a digital conversionsignal Vt, which corresponds to an input digital signal Vin, toconnection lines L1 and L2.

The output stage buffer 20 includes a pair of transistors M5, M6, a pairof resistors 21, 22, and a constant current source 25. For example, thetransistors M5, M6 are N-channel MOS transistors. Their sources areconnected to a positive potential line VDD via the resistors 21, 22.Their drains are mutually interconnected and connected to a referencepotential such as a ground potential via the constant current source 25.The gates of the pair of transistors M5, M6 are connected to connectionlines L1 and L2. The junction between resistor 21 and the source oftransistor M5 and the junction between resistor 22 and the source oftransistor M6 are connected to the output terminal 102 of the buffercircuit 100 via a pair of output lines Lout, respectively. An outputdigital signal Vout such as a digital data signal is output to theoutput terminal 102.

The equalization circuit 30 includes a transistor circuit 31 and aswitch delay circuit 35. It gives a digital inverse signal Vv, which isphase inverted and delayed with respect to the input digital signal Vin,to connection lines L1 and L2. FIG. 2 shows the details of theequalization circuit 30. As shown in FIG. 2, the transistor circuit 31includes two equalization transistor circuits 32, 33. The switch delaycircuit 35 includes two equalization resistor circuits R12, R34, twoequalization capacitor circuits C13, C24, and four switch circuits SW12,SWR34, SWL34, SW56 for switching among the other circuits.

Equalization transistor circuit 32 includes a pair of equalizationtransistors M31, M41. Equalization transistor circuit 33 includes a pairof equalization transistors M32, M42. For example, equalizationtransistors M31, M41, M32, and M42 are all N-channel MOS transistors.Equalization transistors M31 and M41 are both large-size transistorshaving a great channel width CWb. On the other hand, equalizationtransistors M32 and M42 are both smaller-size transistors having a smallchannel width CWs (CWs<CWb).

The sources of equalization transistors M31 and M32 are both connectedto connection line L1. The sources of equalization transistors M41 andM42 are both connected to connection line L2. The drains of equalizationtransistors M31, M41, M32, and M42 are connected to a common line L3.The common line L3 is commonly connected to the drains of transistors M1and M2 of the input stage buffer 10. Gate line 41 g, which is connectedto the gate of equalization transistor M41, and gate line 42 g, which isconnected to the gate of equalization transistor M42, are connected viaselector switch SW1 of switch circuit SW12 to feedback line L4, which isconnected to one pin of the output terminal 102. Gate line 31 g, whichis connected to the gate of equalization transistor M31, and gate line32 g, which is connected to the gate of equalization transistor M32, areconnected via selector switch SW2 of switch circuit SW12 to feedbackline L5, which is connected to the other pin of the output terminal 102.

Equalization resistor circuit R12 is connected to the gate lines 41 g,42 g of equalization transistors M41 and M42 and includes twoequalization resistors R1, R2. The right-hand ends of equalizationresistors R1 and R2 are connected to selector switch SW1 via selectorswitch SWR3 of switch circuit SWR34. The left-hand ends of equalizationresistors R1 and R2 are connected to gate line 42 g of equalizationtransistor M42 via selector switch SWL3 of switch circuit SWL34.Equalization resistor circuit R34 is connected to the gate lines 31 g,32 g of equalization transistors M31 and M32 and includes twoequalization resistors R3, R4. The right-hand ends of equalizationresistors R3 and R4 are connected to selector switch SW2 via selectorswitch SWR4 of switch circuit SWR34. The left-hand ends of equalizationresistors R3 and R4 are connected to gate line 32 g of equalizationtransistor M32 via selector switch SWL4 of switch circuit SWL34.

Equalization resistors R1 and R3 both have a great resistance value Rb,whereas equalization resistors R2 and R4 have a small resistance valueRs (Rs<Rb).

Capacitor equalization circuit C13 includes two equalization capacitorsC1, C3. Capacitor equalization circuit C24 includes two equalizationcapacitors C2, C4. Equalization capacitor C1 is connected between gateline 42 g of equalization transistor M42 and the reference potential.Equalization capacitor C3 is connected between gate line 32 g ofequalization transistor M32 and the reference potential. Equalizationcapacitors C2 and C4 are respectively connected to gate lines 42 g and32 g via selector switches SW5 and SW6 of switch circuit SW56.

Equalization capacitors C1 and C3 both have a great capacitor value Cb,whereas equalization capacitors C2 and C4 have a smaller capacitor valueCs (Cs<Cb).

In the buffer circuit 100 shown in FIG. 1, the amplitude adjustment ofthe digital inverse signal Vv to be provided in the equalization circuit30 is made by switch circuit SW12. In a first state in which selectorswitch SW1 of switch circuit SW12 connects gate line 41 g ofequalization transistor M41 to feedback line L4 and selector switch SW2connects gate line 31 g of equalization transistor M31 to feedback lineL5, equalization transistors M31 and M41 operate to supply digitalinverse signal Vv1 to connection lines L1 and L2. Equalizationtransistors M31 and M41 both have a great channel width CWb and flow arelatively large signal current. Therefore, digital inverse signal Vv1has a great amplitude as indicated by a broken line in FIG. 3B.

On the other hand, in a second state in which selector switch SW1 ofswitch circuit SW12 connects gate line 42 g of equalization transistorM42 to feedback line L4 and selector switch SW2 connects gate line 32 gof equalization transistor M32 to feedback circuit L5, equalizationtransistors M32 and M42 operate to supply digital inverse signal Vv2 toconnection lines L1 and L2. Equalization transistors M32 and M42 bothhave a small channel width CWs and flow a relatively small signalcurrent. Therefore, digital inverse signal Vv2 has a small amplitude asindicated by a solid line in FIG. 3B.

When digital inverse signal Vv1, which has a great amplitude, is addedto the input digital signal Vin, which is shown in FIG. 3A, outputdigital signal Vout1, which is indicated by a broken line in FIG. 3C, isoutput to the output terminal 102. Further, when digital inverse signalVv2, which has a small amplitude, is added to the input digital signalVin, which is shown in FIG. 3A, output digital signal Vout2, which isindicated by a solid line in FIG. 3C, is output to the output terminal102. As described above, the first embodiment adjusts the amplitudes ofdigital inverse signals Vv1 and Vv2 by causing switch circuit SW12 toswitch between the first state in which equalization transistors M31 andM41 operate and the second state in which equalization transistors M32and M42 operate.

The delay amount adjustment to be made by the equalization circuit 30will now be described. Switch circuits SW12, SWR34, SWL34, and SW56 makea switch in order to adjust the delay amount. In a first state in whichselector switches SW1 and SW2 connect gate lines 41 g and 31 g ofequalization transistors M41 and M31 to feedback lines L4 and L5,digital inverse signal Vv is given a small amount of delay, whichresults from the parasitic capacitance values and parasitic resistancevalues of gate lines 41 g and 31 g and feedback lines L4 and L5.

In a second state in which selector switches SW1 and SW2 connect gatelines 42 g and 32 g of equalization transistors M42 and M32 to feedbacklines L4 and L5, the amount of delay provided by equalization resistorcircuits R12 and R34 and capacitor equalization circuits C13 and C24 isadded to the amount of delay provided by the parasitic resistance valuesand parasitic capacitance values of feedback lines L4 and L5.

Equalization resistor circuit R12 is selected by using selector switchSWR3 of switch circuit SWR34 and selector switch SWL3 of switch circuitSWL34. Switch circuits SWR34 and SWL34 are interlocked with each other.Selector switches SWR3 and SWL3 and selector switches SWR4 and SWL4 areinterlocked with each other. When selector switch SWR3 is connected toequalization resistor R1, selector switch SWL3 is also connected toequalization resistor R1, and equalization resistor R1 is connected togate line 42 g of equalization transistor M42. When selector switch SWR3is connected to equalization resistor R1, selector switch SWR4 isconnected to equalization resistor R3. In this instance, selector switchSWL4 is also connected to equalization resistor R3, and equalizationresistor R3 is connected to gate circuit 32 g of equalization transistorM32. Equalization resistors R1 and R3 have a great resistance value Rband give the great resistance value Rb to gate lines 42 g and 32 g ofequalization transistors M42 and M32.

When selector switch SWR3 is connected to equalization resistor R2,selector switch SWL3 is also connected to equalization resistor R2, andequalization resistor R2 is connected to gate line 42 g of equalizationtransistor M42. When selector switch SWR3 is connected to equalizationresistor R2, selector switch SWR4 is connected to equalization resistorR4. In this instance, selector switch SWL4 is also connected toequalization resistor R4, and equalization resistor R4 is connected togate circuit 32 g of equalization transistor M32. Equalization resistorsR2 and R4 have a small resistance value Rs and give the small resistancevalue Rs to gate lines 42 g and 32 g of equalization transistors M42 andM32.

Equalization capacitors C1 and C3 of equalization capacitor circuit C13give a great capacitance Cb to gate lines 42 g and 32 g of equalizationtransistors M42 and M32 at all times. Selector switches SW5 and SW6 ofswitch circuit SW56 connect equalization capacitors C2 and C4 ofequalization capacitor circuit C24 to gate lines 42 g and 32 g ofequalization transistors M42 and M32. When selector switches SW5 and SW6turn ON, a small capacitance Cs is connected in parallel to a greatcapacitance Cb, which is derived from equalization capacitors C1 and C3.

When equalization resistor circuits R12 and R34 give a great resistancevalue Rb, which is derived from equalization resistors R1 and R3, andequalization capacitor circuit s C13 and C24 give a great capacitanceCb+Cs, which is obtained with equalization capacitors C1 and C3connected in parallel to equalization capacitors C2 and C4, the maximumdelay amount is given to gate lines 42 g and 32 g of equalizationtransistors M42 and M32. When equalization resistor circuits R12 and R34give a small resistance value Rs, which is derived from equalizationresistors R2 and R4, and equalization capacitor circuit C13 gives anequalization capacitance Cs, which is derived from equalizationcapacitors C1 and C3, the minimum delay amount is given to gate lines 42g and 32 g of equalization transistors M42 and M32.

A delay amount midway between the maximum delay amount and minimum delayamount is given in a state where equalization resistor circuits R12 andR34 give a large resistance value Rb, which is derived from equalizationresistors R1 and R3, and equalization capacitor circuit s C13 and C24give an equalization capacitance Cb, which is derived from equalizationcapacitors C1 and C3, and in a state where equalization resistorcircuits R12 and R34 give a small resistance value Rs, which is derivedfrom equalization resistors R2 and R4, and equalization capacitorcircuit s C13 and C24 give a great capacitance Cb+Cs, which is derivedfrom equalization capacitors C1, C3, C2, and C4. When different midwayamounts are given, a total of four different delay amounts areselectable.

When the delay amount of the equalization circuit 30 is selectivelyused, a change emphasis timing adjustment can be made on the outputdigital signal Vout as indicated in FIGS. 4A, 4B, and 4C. FIG. 4A showsthe input digital signal Vin. FIG. 4B shows digital inverse signals Vv3and Vv4, which are derived from two typical delay amounts such as theabove-mentioned maximum delay amount and minimum delay amount. FIG. 4Cshows output digital signals Vout3 and Vout4. When digital inversesignal Vv3, which has the maximum delay amount that is indicated by abroken line in FIG. 4B, is selected, output digital signal Vout3, whichis indicated by a broken line in FIG. 4C, is obtained. When digitalinverse signal Vv4, which has the minimum delay amount that is indicatedby a solid line in FIG. 4B, is selected, output digital signal Vout4,which is indicated by a solid line in FIG. 4C, is obtained.

As described above, the digital signal buffer circuit 100 according tothe first embodiment selects a digital inverse signal Vv whose amplitudelevel and delay amount are adjusted by making a selection with switchcircuits SW12, SWR34, SWL34, and SW56 of the equalization circuit 30,and emphasizes a change in the output digital signal Vout whileadjusting it in accordance with the amplitude level and frequency of thedigital signal to be transmitted.

SECOND EMBODIMENT

In the first embodiment shown in FIG. 2, a third state maybe given toselector switches SW1 and SW2 of switch circuit SW12 in addition to theabove-mentioned first state and second state. In the third state, gatelines 31 g and 41 g of equalization transistors M31 and M41 areconnected to feedback lines L4 and L5, and gate lines 32 g and 42 g ofequalization transistors M32 and M42 are also connected to feedbacklines L4 and L5.

Selector switches SW1 and SW2, which provides the third state inaddition to the first state and second state, can be implemented byusing a transfer gate circuit TG as indicated in FIG. 5. The transfergate circuit TG includes transfer gates TG1 and TG2. Transfer gate TG1is obtained by arranging an N-channel MOS transistor NMOS1 and aP-channel MOS transistor PMOS1 in parallel to each other. It turns OFFwhen a control gate NG1 of the N-channel MOS transistor NMOS1 is at alow level (L level) and a control gate PG1 of the P-channel MOStransistor PMOS1 is at a high level (H level). It turns ON when thecontrol gate NG1 of the N-channel MOS transistor NMOS1 is at a highlevel (H level) and the control gate PG1 of the P-channel MOS transistorPMOS1 is at a low level (L level).

Transfer gate TG2 is obtained by arranging an N-channel MOS transistorNMOS2 and a P-channel MOS transistor PMOS2 in parallel to each other. Itturns OFF when a control gate NG2 of the N-channel MOS transistor NMOS2is at a low level (L level) and a control gate PG2 of the P-channel MOStransistor PMOS2 is at a high level (H level). It turns ON when thecontrol gate NG2 of the N-channel MOS transistor NMOS2 is at a highlevel (H level) and the control gate PG2 of the P-channel MOS transistorPMOS2 is at a low level (L level).

The transfer gate circuit TG forms selector switch SW1 by connecting theright-hand terminals for transfer gates TG1 and TG2 to feedback line L4,connecting the left-hand terminal for transfer gate TG1 to gate line 41g of equalization transistor M41, and connecting the left-hand terminalfor transfer gate TG2 to selector switch SWR3.

Another transfer gate circuit TG, which looks like FIG. 5, is alsofurnished to form selector switch SW2 by connecting the right-handterminals for transfer gates TG1 and TG2 of the transfer circuit TG tofeedback line L5, connecting the left-hand terminal for transfer gateTG1 to gate line 31 g of equalization transistor M31, and connecting theleft-hand terminal for transfer gate TG2 to selector switch SWR4.

When the transfer gate circuits TG form selector switches SW1 and SW2 asdescribed above, selector switches SW1 and SW2 can be individuallyoperated in the first state, second state, and third state.

In the third state, equalization transistors M32 and M42 operate inparallel with equalization transistors M31 and M41 so that the digitalinverse signal Vv has an amplitude that is intermediate between theamplitudes of signals Vv1 and Vv2, which are shown in FIG. 3B. Further,the output digital signal Vout also has an amplitude that isintermediate between the amplitudes of signals Vout1 and Vout2, whichare shown in FIG. 3C.

In the third state of switch circuit SW12, the delay amount of thedigital inverse signal Vv can be adjusted in four steps at theabove-mentioned intermediate level by making a selection with switchcircuits SWR34, SWL34, and SW56.

THIRD EMBODIMENT

In a third embodiment, selector switches SW1 and SW2 for the firstembodiment are formed by the transfer gates TG shown in FIG. 5, andselector switches SWR3, SWL3, SWR4, and SWL4 are formed by the transfergates TG shown in FIG. 5.

In the third embodiment, selector switches SWR3 and SWL3 are formed bythe transfer gates TG shown in FIG. 5 so that a resistance value derivedfrom a parallel connection between equalization resistors R1 and R2 canbe given to gate line 42 g of equalization transistor M42. Further,selector switches SWR4 and SWL4 are formed by the transfer gates TGshown in FIG. 5 so that a resistance value, derived from a parallelconnection between equalization resistors R3 and R4, can be given togate line 32 g of equalization transistor M32. As a result, the delayamount can be adjusted in an increased number of steps.

FOURTH EMBODIMENT

FIG. 6 illustrates a fourth embodiment of the digital signal buffercircuit according to the present invention. The buffer circuit 100Aaccording to the fourth embodiment includes three buffers 51, 52, 53,two low-pass filters 55, 56, and selector switches SW7, SW8. Buffer 51is an input stage buffer, configured the same as the input stage buffer10 shown in FIG. 1, and includes transistors M1 and M2. This input stagebuffer 51 is connected to the input terminal 101 via an input line Lin.Buffer 53 is an output stage buffer, configured the same as the outputstage buffer 20 shown in FIG. 1, and includes transistors M5 and M6.This output stage buffer 53 is connected to the output terminal 102 viaan output line Lout. Buffer 52 is an intermediate buffer and connectedbetween the input stage buffer 51 and output stage buffer 53. Theintermediate buffer 52 is connected to the input stage buffer 51 viaconnection line L11. Further, the intermediate buffer 52 is connected tothe output stage buffer 53 via connection line L12.

The intermediate buffer 52 is a combination of the input stage buffer 10and equalization circuit 30, which are shown in FIG. 1. The intermediatebuffer 52 comprises the transistor circuit 31 shown in FIG. 2. Thetransistor circuit 31 includes transistor equalization circuits 32 and33. Equalization transistor circuit 32 has equalization transistors M31and M41, which have a great gate width. Equalization transistor circuit33 has equalization transistors M41 and M42, which have a small gatewidth. Either of these equalization transistor circuits 32, 33 is switchselected.

The low-pass filters 55, 56 have different resistance values andcapacitance values so as to give different delay amounts. Low-passfilter 55 is positioned in feedback line L21, which is betweenconnection line L12 and the gate circuits of equalization transistorcircuits 32 and 33 of the intermediate buffer 52. Low-pass filter 56 ispositioned in feedback line L22, which is between the output line Loutand the gate circuits of equalization transistor circuits 32 and 33 ofthe intermediate buffer 52. Selector switch SW7 is connected betweenlow-pass filter 55 and equalization transistor circuits 32 and 33 of theintermediate buffer 52. Selector switch SW8 is connected betweenlow-pass filter 56 and equalization transistor circuits 32 and 33 of theintermediate buffer 52.

When selector switches SW7 and SW8 are connected to low-pass filter 55,low-pass filter 55 is connected to the gate circuit of equalizationtransistor circuit 32 or 33 of the intermediate buffer 52 so that thedelay amount of low-pass filter 55 is given from connection line L12,which is between the intermediate buffer 52 and output buffer 53, to adigital data signal that is fed back via feedback line L21. Whenselector switches SW7 and SW8 are connected to low-pass filter 56, onthe other hand, the delay amount of low-pass filter 56 is given from theoutput line Lout to a feedback digital data signal that is fed back viafeedback line L22, which is routed to equalization transistor circuit 32or 33 of the intermediate buffer 52.

In accordance with switching between feedback lines L21 and L22 andswitching between low-pass filters 55 and 56, the amplitude and delayamount of the digital inverse signal Vv can be adjusted.

FIFTH EMBODIMENT

FIG. 7 illustrates a fifth embodiment of the digital signal buffercircuit according to the present invention. The buffer circuit 100Baccording to the fifth embodiment includes an input stage buffer 61 andan output stage buffer 63. The input stage buffer 61 is configured thesame as the input stage buffer 10 shown in FIG. 1 and includestransistors M1 and M2. The output stage buffer 63 is a combination ofthe input stage buffer 10 shown in FIG. 1 and the transistor circuit 31shown in FIG. 2 and includes equalization transistor circuits 32 and 33.The input stage buffer 61 and output stage buffer 63 are connected withconnection line L31.

A delay path 65, which is configured in a feed-forward manner, is formedbetween the input stage buffer 61 and the transistor circuit 31 of theoutput stage buffer 63. The feed-forward delay path 65 is formed betweenthe input stage buffer 61 and the gate circuits of equalizationtransistor circuits 32 and 33 in the output stage buffer 63.

The delay path 65 includes an intermediate buffer 62, a switch SW9, anda low-pass filter 66. When switch SW9 turns ON, the intermediate buffer62 supplies a digital inverse signal Vv in a feed-forward manner to thegate circuits of equalization transistor circuits 32 and 33, which areincluded in the output stage buffer 63. A delay is given to this digitalinverse signal Vv by low-pass filter 66.

The fifth embodiment supplies a digital inverse signal Vv in afeed-forward manner and uses low-pass filter 66 to set its delay amount.

The digital signal buffer circuit according to the present invention isused in a digital signal communication system based on a transmissionpath, for instance, to emphasize a digital data change at a receivingend or transmitting end.

The major benefits of the present invention described above aresummarized as follows:

The digital signal buffer circuit according to the present invention canadjust the amplitude level and delay amount of a digital inverse signalthat is obtained by inverting an input digital signal and delayed.Therefore, it is possible to adjust the amplitude level and delay amountof the digital inverse signal in accordance with input digital signalshaving different amplitudes and frequencies, and generates an outputdigital signal in which a change is effectively emphasized. It is alsopossible to easily correct changes in the characteristic in a digitalsignal buffer circuit manufacturing process.

1. A digital signal buffer circuit, comprising: an equalization circuitfor generating a digital inverse signal that is delayed from an inputdigital signal and obtained by inverting said input digital signal,wherein said equalization circuit includes a plurality ofvariously-sized equalization transistors, a delay circuit capable ofchanging the delay amount, and a switching circuit for switching betweensaid plurality of transistors and changing the delay amount of saiddelay circuit.
 2. The digital signal buffer circuit according to claim1, wherein said switching circuit includes a first switch for switchingbetween said plurality of transistors and a second switch for changingthe delay amount of said delay circuit.
 3. The digital signal buffercircuit according to claim 2, wherein said first switch comprises atransfer gate circuit.
 4. The digital signal buffer circuit according toclaim 2, wherein said first switch and said second switch both comprisea transfer gate circuit.
 5. The digital signal buffer circuit accordingto claim 1, wherein said delay circuit includes a plurality ofequalization resistors having different resistance values and aplurality of equalization capacitors having different capacitancevalues, and wherein the delay amount is changed by switching between theplurality of equalization resistors and between the plurality ofequalization capacitors.
 6. The digital signal buffer circuit accordingto claim 5, wherein said switching circuit includes a third switch forswitching between said plurality of equalization resistors and a fourthswitch for switching between said plurality of equalization capacitors.7. The digital signal buffer circuit according to claim 1, furthercomprising: an input stage buffer for letting the gates of a pair oftransistors receive an input digital signal and an output stage bufferfor letting the gates of a pair of transistors receive the output ofsaid input stage buffer, wherein a plurality of transistors in saidequalization circuit receive the output of said output stage buffer andapply said digital inverse signal to the gates of the transistors ofsaid output stage buffer.
 8. A digital signal buffer circuit,comprising: a first buffer for receiving an input digital signal; asecond buffer for receiving the output of said first buffer; and a thirdbuffer for generating an output digital signal upon receipt of an outputfrom said second buffer, wherein said second buffer includes anequalization transistor, which generates a digital inverse signal thatis obtained by inverting said input digital signal and delayed, andswitches between a first feedback line for feeding the output of saidsecond buffer back to said equalization transistor and a second feedbackline for feeding the output of said third buffer back to saidequalization transistor.
 9. The digital signal buffer circuit accordingto claim 8, wherein said first feedback line and said second feedbackline are connected to low-pass filters that provide different delayamounts.
 10. A digital signal buffer circuit, comprising: a first bufferfor receiving an input digital signal; and a second buffer forgenerating an output digital signal upon receipt of an output from saidfirst buffer, wherein said second buffer includes an equalizationtransistor for generating a digital inverse signal that is obtained byinverting said input digital signal and delayed; and wherein a delaypath, which includes a switch and a low-pass filter, is formed betweenthe output of said first buffer and said equalization transistor.